Title :
Toward Amp-Level Field Emission With Large-Area Arrays of Pt-Coated Self-Aligned Gated Nanoscale Tips
Author :
Fomani, Arash A. ; Guerrera, Stephen A. ; Velasquez-Garcia, L.F. ; Akinwande, Akintunde Ibitayo Tayo
Author_Institution :
Microsyst. Technol. Labs., Massachusetts Inst. of Technol., Cambridge, MA, USA
Abstract :
Design, fabrication, and characterization of Pt-coated, self-aligned, and gated Si field emission arrays are reported. Arrays of 320000 tips with 10 μm pitch are employed to emit currents as high as 0.35 A (current density of 1.1 A/cm2) at gate-emitter biases of 300 V. For reliability, the devices have a gate dielectric thicker than 2.5 μm maintaining the field inside gate insulator below 150 V/μm and a 5-nm-thick Pt-coating protecting the tips against sputtering by back-streaming ions. The Pt-coating also increases the capture cross section of electrons from the emitter cone, resulting in higher emission currents compared with uncoated Si tips when the supply of electrons is limited to the surface. The device failure at high currents is associated with plasma ignition due to local pressure rise caused by outgassing of the anode. At lower emission currents, the devices are capable of long-term emission (>3 h) at pressures as high as 10-5 Torr. Furthermore, a high-yield fabrication process is presented for large-area fabrication of highly-uniform gated tip arrays that could be expanded to active areas larger than 10 cm2 to increase the emission current.
Keywords :
anodes; elemental semiconductors; failure analysis; field emitter arrays; platinum; protective coatings; reliability; silicon; Pt; Si; amp-level field emission; anode outgassing; back-streaming ions; device failure; electron capture cross section; emission currents; emitter cone; field inside gate insulator; gate dielectric; gated silicon field emission arrays; high-yield fabrication process; highly-uniform gated tip arrays; large-area arrays; large-area fabrication; local pressure rise; plasma ignition; platinum-coated field emission arrays; platinum-coated self-aligned gated nanoscale tips; protective coating; reliability; self-aligned field emission arrays; size 5 nm; sputtering; voltage 300 V; Anodes; Dielectrics; Etching; Fabrication; Logic gates; Silicon; Electron sources; field emission; gated tip arrays; self-aligned structures; vacuum electronic devices; vacuum electronic devices.;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2014.2322518