DocumentCode
387615
Title
Track assignment: a desirable intermediate step between global routing and detailed routing
Author
Batterywala, Shabbir ; Shenoy, Narendra ; Nicholls, William ; Zhou, Hai
Author_Institution
Synopsys Inc., Mountain View, CA, USA
fYear
2002
fDate
10-14 Nov. 2002
Firstpage
59
Lastpage
66
Abstract
Routing is one of the most complex stages in the back-end design process. Simple routing algorithms based on two stages of global routing and detailed routing do not offer appropriate opportunities to address problems arising from signal delay, cross-talk and process constraints. An intermediate stage of track assignment between global and detailed routing proves to be an ideal place to address these problems. With this stage it is possible to use global routing information to efficiently address these problems and to aid the detailed router in achieving the wiring completions. In this paper we formulate routing as a three stage process; global routing, track assignment and detailed routing. We describe the intermediate track assignment problem and suggest an efficient heuristic for its solution. We introduce cost metrics to model basic effects arising from connectivity. We discuss extensions to include signal integrity and process constraints. We propose a heuristic based on weighted bipartite matching as a core routine. To improve its performance additional heuristics based on lookahead and segment splitting are also suggested. Experimental results are given to highlight the efficacy of the track assignment stage in the routing process.
Keywords
VLSI; circuit layout CAD; crosstalk; integrated circuit interconnections; integrated circuit layout; network routing; back-end design process; connectivity; cost metrics; cross-talk; detailed routing; global routing; intermediate track assignment heuristic; lookahead heuristic; process constraints; routing algorithms; segment splitting heuristic; signal delay; signal integrity; three stage routing process; track assignment; weighted bipartite matching heuristic; wiring completions; Costs; Crosstalk; Delay; Pins; Process design; Routing; Signal processing; Very large scale integration; Wire; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on
ISSN
1092-3152
Print_ISBN
0-7803-7607-2
Type
conf
DOI
10.1109/ICCAD.2002.1167514
Filename
1167514
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