Title :
SAT and ATPG: Boolean engines for formal hardware verification
Author :
Biere, Armin ; Kunz, Worfgng
Author_Institution :
Dept. of Comput. Sci., Eidgenossische Tech. Hochschule, Zurich, Switzerland
Abstract :
In this survey, we outline basic SAT- and ATPG-procedures as well as their applications in formal hardware verification. We attempt to give a path through the literature and provide a basic orientation concerning the problem formulations and known approaches in this active field of research.
Keywords :
Boolean functions; automatic test pattern generation; circuit analysis computing; computability; formal verification; ATPG; Boolean engines; SAT; combinational equivalence checking; conjunctive normal form; formal hardware verification; property checking; satisfiability; Application software; Automatic test pattern generation; Circuit faults; Circuit testing; Computer science; Electronic design automation and methodology; Engines; Equations; Fault location; Hardware;
Conference_Titel :
Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on
Print_ISBN :
0-7803-7607-2
DOI :
10.1109/ICCAD.2002.1167620
