An investigation into the efficiency of a parallel TMS320 architecture: DFT and speech filterbank applications

This paper analyzes a particular parallel architecture which incorporates eight Texas Instruments TMS32010 digital signal processors. The fully built and operational multiprocessor system, named PT8, is described, and several common DSP algorithms are presented which illustrate its characteristics. It is shown that data handling considerations are the major factors in the performance of these algorithms. Suggestions for upgrading this architecture to one which manages data more efficiently are given.