A high-speed programmable architecture using barrel shifters for FFT and digital filtering

Multiply and accumulate are the two basic operations for FFT and digital filtering algorithms. In high-speed applications, the multiplier is crucial to the performance. The multiplier requires either large chip area if parallel implementation is used or large amount of time if serial architecture is used. In this paper, the design of basic FFT arithmetic element and FIR filters using barrel shifters and accumulators (BSAC) to perform the multiplications is proposed and studied. The resulting architecture is completely programmable and allows the use of variable number of basic cells for each coefficient. The throughput rate of such an architecture is determined only by the delay in a single cell and hence can be of the order of 100 MHz or higher.