DocumentCode
388326
Title
Application of the PDSP chip set to LPC synthesis
Author
Dorsey, Eric ; Caldwell, Jim
Author_Institution
Telesensory Speech Systems, Palo Alto, California
Volume
6
fYear
1981
fDate
29677
Firstpage
382
Lastpage
385
Abstract
Due to its programmability, the Programmable Digital Signal Processor (PDSP)chip set lends itself to the implementation of a variety of speech synthesis functions. When programmed as an all-pole lattice filter used in LPC synthesis, the PDSP allows the user to exploit quality-enhancement techniques such as mixed sourcing, pitch- or time-synchronous updating, variable frame and filter length, interpolation, various quantizing schemes, and adjustable speaking rate. Since the quantizing algorithm is under user control, the encoded bit rate may range from 1100 to 28,000 bits per second according to speech quality requirements. The paper discusses these techniques and a commercially available LPC speech synthesis circuit board which illustrates typical PDSP application.
Keywords
Bit rate; Digital signal processors; Filters; Interpolation; Lattices; Linear predictive coding; Printed circuits; Signal processing algorithms; Signal synthesis; Speech synthesis;
fLanguage
English
Publisher
ieee
Conference_Titel
Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '81.
Type
conf
DOI
10.1109/ICASSP.1981.1171276
Filename
1171276
Link To Document