An expandable single-IC digital filter/Correlator

The commercial success of single-integrated circuit multipliers and correlators has prompted the design of a new integrated circuit for video-speed digital convolution and correlation. This device is based on two concepts: 1.) the merging of delay and pipeline registers and 2.) "bit-slicing" the filter array in both the signal data word and coefficient dimensions. The device can update one coefficient per clock cycle. The result is an expandable "building block" which can be cascaded or paralleled to give the desired length, signal data word length, and coefficient data word length for any desired filter up to 20 MSPS.