Improving ILP with instruction-reuse cache hierarchy

Instruction reuse is an interesting strategy for improving processor performance. Several techniques at fine and coarse granularities have been proposed to extend instruction reuse. Among them block and trace reuse are the most promising. This work studies the benefits of combining block and trace reuse with instruction reuse to form an instruction reuse cache hierarchy. A simple reuse hierarchy is implemented and tested with select SPEC95 benchmarks. Both instruction reuse and ILP show modest performance improvements when compared to the base schemes. Within the scope of the selected benchmarks, the proposed reuse policy reuses as much as 60% of possible reusable instructions and shows an average ILP gain of 13.83%. This paper introduces the proposed reuse model and its simulation. The simulation results are presented and analyzed. Finally, future research directions in this area have been discussed.