Multiplierless realization of all pole digital filters

This paper considers a low-sensitivity structure that is more suitable for all-pole digital filters for feasibility of multiplierless implementation. In this structure the multiplier coefficients are found to be quite small. These coefficients after conversion to minimum signed powers of two (MNSPT) or canonic signed digit (CSD) forms are implemented in a multiplierless manner, i.e., by bit shifts and adds and/or subtracts. It is seen that the required number of nonzero bits for the coefficients in such cases are quite low. Further, if we allow a marginal deviation in specification, or start with a design of marginally stricter specifications than the desired specifications without any increase in the filter order, the requirement of number of nonzero bits becomes quite low, making the overall realization scheme quite attractive.