Title :
Pipelined design of the high-speed RSA encryption processor with built-in table for residue calculation of redundant binary numbers
Author :
Tomabechi, Nobuhiro ; Ito, Teruki
Author_Institution :
Hachinohe Inst. of Technol., Japan
Abstract :
In this paper, a high-speed RSA encryption processor employing a highly parallel architecture based on the redundant binary number arithmetic, table-look-up, and pipelining is presented. It is demonstrated that the encryption time of the presented processor is about 1/12 that of conventional processors and that the encryption rate for continuous input data is about 3/2 that of conventional processors.
Keywords :
parallel architectures; pipeline arithmetic; public key cryptography; residue number systems; table lookup; telecommunication security; built-in table; communication security; encryption rate; high-speed RSA encryption processor; highly parallel architecture; pipelined design; pipelining; redundant binary number arithmetic; residue calculation; table-look-up; Arithmetic; Computer networks; Cryptography; Delay effects; Hardware; Parallel architectures; Pipeline processing; Process design; Prototypes; Timing;
Conference_Titel :
TENCON '02. Proceedings. 2002 IEEE Region 10 Conference on Computers, Communications, Control and Power Engineering
Print_ISBN :
0-7803-7490-8
DOI :
10.1109/TENCON.2002.1181301
