Baseband ASIP design for SDR

Baseband ASIP designs for handsets are discussed based on the author´s R&D backgrounds. Algorithms for 4G, 3G, and WLAN are analyzed and selected for implementation based on the trade off of cost and performance with power consumption in mind. A SDR ASIP baseband system architecture is proposed for 4G and 3G mobile handsets. Function partitions for heterogeneous symbol processors are introduced to get higher performance over cost. Three structures for DFE, FFE, and Matrix symbol ASIP are proposed. The concept of bit parallel processor is introduced. Challenges of baseband processors for UDN of 5G were briefly introduced. Conclusions on ASIP architecture and system design are given for different baseband processors on different products.