Title :
MAP decoder architecture: soft IP for SOC applications
Author :
El-Assal, Mahmoud ; Bayoumi, Magdy
Author_Institution :
Center For Adv. Comput. Studies, Louisiana Univ., Lafayette, LA, USA
Abstract :
A soft IP for MAP decoder is presented. The Soft IP supports different design objectives, such as high performance and area efficiency. System parameters and required performance configure the IP yielding the architecture. The IP is realized using VHDL and scripts that accept design specification from the designer and automatically generate a synthesizable HDL. FPGA platform is used for rapidly prototyping the IP core. Prototyping adhering the third generation standard yields architectures range from 56 Kbps up to 20 Mbps.
Keywords :
decoding; field programmable gate arrays; hardware description languages; industrial property; logic CAD; system-on-chip; 56 Kbit/s to 20 Mbit/s; FPGA platform; MAP decoder architecture; SOC applications; VHDL; design objectives; design specification; soft IP; synthesizable HDL; system parameters; third generation standard; Application software; Computer architecture; Decoding; Design methodology; Error correction codes; Field programmable gate arrays; Hardware design languages; Process design; Prototypes; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Print_ISBN :
0-7803-7523-8
DOI :
10.1109/MWSCAS.2002.1186806
