A low-power VLSI design of an HMM based speech recognition system

Author

Yoshizawa, S. ; Miyanaga, Y. ; Wada, N.

Author_Institution

Graduate Sch. of Eng., Hokkaido Univ., Sapporo, Japan

Volume

2

fYear

2002

fDate

4-7 Aug. 2002

Abstract

This paper reports a low-power VLSI design of a HMM based speech recognition system. Output probability calculation is the most computationally expensive part of continuous HMM (CHMM) based speech recognition. The proposed architecture calculates the output probability with parallel and pipeline processing. It enables to reduce memory access and have high computing efficiency. The novel point is the efficient use of register arrays that reduce memory access considerably compared with any conventional method. The implemented system can achieve a real time response with lower clock in a middle size vocabulary recognition task (100-1000 words) by using this technique.

Keywords

VLSI; hidden Markov models; low-power electronics; parallel processing; pipeline processing; probability; speech recognition; CHMM; HMM based speech recognition system; low-power VLSI design; memory access; middle size vocabulary recognition task; output probability calculation; parallel processing; pipeline processing; real time response; register arrays; Clocks; Computer architecture; Hidden Markov models; Pipeline processing; Probability; Real time systems; Registers; Speech recognition; Very large scale integration; Vocabulary;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on

Print_ISBN

0-7803-7523-8

Type

conf

DOI

10.1109/MWSCAS.2002.1186905

Filename

1186905