Title :
Adaptive design method for efficient direct digital synthesis
Author :
Bruce, J.W. ; Creekmore, J.E. ; Blalock, B.J.
Author_Institution :
Dept. of Electr. & Comput. Eng., Mississippi State Univ., MS, USA
Abstract :
In this paper, an area and power efficient ROM-less DDFS circuit with sinusoidal output is proposed. Sinusoidal spaced reference voltages are generated using an integrated resistor with a complex geometry. A DDFS accumulator output controls the nonlinear sinusoidal DAC directly and without the power-hungry ROM. The proposed design is independent of sheet resistance, and voltage reference power dissipation can be tailored to the application. Photolithography limitations can introduce geometry errors, thus, reference voltage errors. An adaptive design algorithm is proposed that reduces reference errors by more than an order of magnitude compared to the prior method. Finally, measurement results from a prototype 0.5 μm CMOS implementation are presented.
Keywords :
CMOS digital integrated circuits; circuit CAD; direct digital synthesis; integrated circuit design; 0.5 micron; CMOS implementation; DDS accumulator; adaptive design method; area efficient ROM-less DDS circuit; direct digital synthesis; integrated resistor; nonlinear sinusoidal DAC; power efficient ROM-less DDS circuit; reference voltage errors reduction; sinusoidal output; sinusoidal spaced reference voltages; voltage reference power dissipation; Algorithm design and analysis; Design methodology; Electrical resistance measurement; Geometry; Integrated circuit synthesis; Lithography; Power dissipation; Read only memory; Resistors; Voltage;
Conference_Titel :
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Print_ISBN :
0-7803-7523-8
DOI :
10.1109/MWSCAS.2002.1186919
