DocumentCode :
391859
Title :
SPPV: a new formal verification environment
Author :
Ivanov, Lubomir ; Shute, Michael
Author_Institution :
Dept. of Comput. Sci., Iona Coll., New Rochelle, NY, USA
Volume :
1
fYear :
2002
fDate :
4-7 Aug. 2002
Abstract :
Formal verification has become an integral part of the product development cycle leading to a demand for powerful, yet easy to use tools, which conceal the complexity of the underlying mathematical arguments through the use of convenient interfaces and automatic verification. In this paper we present a new formal verification environment-SPPV-based on series-parallel poset verification. SPPV allows fast, automated verification of event sequencing in complex systems. The system model and properties can be expressed as series-parallel poset expressions or in Verilog.
Keywords :
formal verification; hardware description languages; product development; SPPV; Verilog; automatic verification; complex systems; event sequencing; formal verification environment; product development cycle; series-parallel poset verification; system model; Bismuth; Computational modeling; Computer simulation; Educational institutions; Formal verification; Hardware design languages; Power system modeling; Product development; Protocols; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Print_ISBN :
0-7803-7523-8
Type :
conf
DOI :
10.1109/MWSCAS.2002.1187180
Filename :
1187180
Link To Document :
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