SPPV: a new formal verification environment

Formal verification has become an integral part of the product development cycle leading to a demand for powerful, yet easy to use tools, which conceal the complexity of the underlying mathematical arguments through the use of convenient interfaces and automatic verification. In this paper we present a new formal verification environment-SPPV-based on series-parallel poset verification. SPPV allows fast, automated verification of event sequencing in complex systems. The system model and properties can be expressed as series-parallel poset expressions or in Verilog.