Title :
Test optimization of bus-structured SoCs using embedded processor
Author :
Tehranipour, M.H. ; Nourani, M. ; Fakhraie, S.M. ; Papachristou, C.A.
Author_Institution :
Dept. of Electron. Eng., Texas Univ., Richardson, TX, USA
Abstract :
Embedded processors are now widely used in system-on-chips. This paper presents an optimization technique for testing a bus-structured system using an embedded processor.We present a systematic approach for test access mechanism that allows processor to access all cores with minimum overhead. We show an ILP formulation to minimize the test schedule. The method requires negligible overhead but provides great flexibility in terms of access mechanism and future reuse.
Keywords :
embedded systems; integer programming; integrated circuit testing; linear programming; microprocessor chips; system-on-chip; bus-structured system; embedded processor; integer linear programming; system-on-chip; test access mechanism; test optimization; Built-in self-test; Circuit testing; Digital signal processing chips; Intellectual property; Logic testing; Processor scheduling; Protection; Software testing; System testing; Test pattern generators;
Conference_Titel :
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Print_ISBN :
0-7803-7523-8
DOI :
10.1109/MWSCAS.2002.1187183
