Analysis of DLL jitter due to substrate noise

Substrate noise is the major source of performance limitation in mixed-signal integrated circuits. This paper studies substrate noise effects on the performance of delay-locked loops (DLLs). Due to their robust noise performance, the delay-locked-loops are widely used as clock generators of microprocessors. Although exploiting advanced circuit techniques reduces the timing jitter induced by the substrate noise to a large extent, the hostile noisy digital section in a mixed-signal VLSI circuit can still cause a large substrate noise and hence a non-negligible timing jitter in DLL clock generators. In this paper a new stochastic model for the substrate noise is proposed This model is then utilized to derive the phase noise of the voltage-controlled delay line (VCDL) inside the loop. The DLL timing jitter is predicted in response to the VCDL phase not. se. A comparison between the results obtained by our mathematical model and those obtained using HSPICE verifies our proposed model.