A parallel digital architecture for delta-sigma modulation

A major drawback of delta-sigma modulation is the high oversampling ratios required, especially for single-bit quantization. Accordingly, much of the research in the area has focused on lowering the sampling rate through various parallelization approaches. However, this research has been overwhelmingly concentrated on continuous and discrete-time analog modulator implementations for A/D converters, and not on reducing the critical path in a digital implementation for D/A conversion. In this paper the popular time-interleaved modulator is paired with a vector quantizer implementation of a finite-length modulator to form a parallel implementation of a delta-sigma DAC with a reduced critical path.