Minimizing the number of registers and the number of phases in synchronous digital designs with minimal clock period

Methods based on modulo scheduling for software pipelining have been recently proposed to minimize the clock period of synchronous digital designs. These methods can be framed in the following four steps process: in Step 1, the minimal clock period P has to be determined; in Step 2, a valid periodic schedule of the computational elements is computed; in Step 3, registers are inserted in the circuit according to the computed schedule; in Step 4, phases to control registers are determined. In this process, the challenge is how to realize steps 2, 3 and 4 in order to minimize the number of registers and the number of phases. In this paper, we address the problem of computing a valid periodic schedule of the computational elements, and placing registers while minimizing the number of registers and the number of phases. We propose a mathematical formulation to this problem, and a mixed integer linear program to solve it. We present preliminary experimental results to show the effectiveness of the proposed approach.