Title :
Channel height estimation in VLSI design
Author :
Li, Lun ; Manikas, Theodore W. ; Jin, He
Author_Institution :
Dept. of Electr. Eng., Tulsa Univ., OK, USA
Abstract :
This paper presents four methods to estimate channel height for congestion analysis in VLSI design automation. Our channel height estimation methods consider constraint graphs and net types in a channel. The experimental results show that the proposed methods yield better results than existing methods.
Keywords :
VLSI; constraint handling; graphs; integrated circuit interconnections; integrated circuit layout; VLSI design automation; VLSI layout; channel height estimation; channel net types; constraint graphs; Algorithm design and analysis; Circuits; Delay; Design automation; Equations; Routing; State estimation; Time to market; Transistors; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Print_ISBN :
0-7803-7523-8
DOI :
10.1109/MWSCAS.2002.1187295
