DocumentCode
39234
Title
Reachability-Based Robustness Verification and Optimization of SRAM Dynamic Stability Under Process Variations
Author
Yang Song ; Hao Yu ; DinakarRao, Sai Manoj Pudukotai
Author_Institution
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore
Volume
33
Issue
4
fYear
2014
fDate
Apr-14
Firstpage
585
Lastpage
598
Abstract
The dynamic stability margin of SRAM is largely suppressed at nanoscale due to not only dynamic noise but also process variation. This paper introduces an analog verification for SRAM dynamic stability under threshold-voltage variations. A zonotope-based reachability analysis by the backward Euler method is deployed for SRAM dynamic stability in state space with consideration of SRAM nonlinear dynamics. It can simultaneously consider multiple SRAM variation sources without multiple repeated computations. What is more, sensitivity analysis is developed for zonotope to optimize SRAM designs departing from unsafe regions by simultaneously tuning multiple SRAM device parameters. In addition, compared to the SRAM optimization by single-parameter small-signal sensitivity, the proposed method can converge faster with higher accuracy. As shown by numerical experiments, the proposed optimization method can achieve 600× speedup on average when compared to the repeated Monte Carlo simulations under the similar accuracy.
Keywords
SRAM chips; circuit optimisation; circuit stability; integrated circuit design; nanoelectronics; reachability analysis; sensitivity analysis; Monte Carlo simulations; SRAM designs; SRAM dynamic stability optimization; SRAM nonlinear dynamics; analog verification; backward Euler method; dynamic noise; dynamic stability margin; multiple SRAM device parameter tuning; multiple SRAM variation sources; process variations; reachability-based robustness verification; single-parameter small-signal sensitivity analysis; threshold-voltage variations; zonotope-based reachability analysis; Optimization; Random access memory; Reachability analysis; Robustness; Safety; Stability analysis; Transistors; Design for manufacturability; memory; mixed-mode; performance optimization; simulation; transistor-sizing;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/TCAD.2014.2304704
Filename
6774560
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