Title :
Logic synthesis of multi-output functions for PAL-based CPLDs
Author_Institution :
Inst. of Electron., Silesian Univ. of Technol., Gliwice, Poland
Abstract :
In this paper multi-level synthesis for PAL-based CPLDs is presented. The essence of the method is to search for multi-output implicants that can be shared by several functions. This approach presents a unique form for illustrating a minimized form of a multi-output Boolean function. The presented method, implemented within the PALDec system, is based on the analysis of graph nodes that represent states of a digital circuit outputs. The results of synthesis for benchmarks are compared to the classical technology mapping method.
Keywords :
Boolean functions; graph theory; logic CAD; minimisation of switching nets; programmable logic devices; PAL-based CPLDs; PALDec system; digital circuit outputs; graph nodes; logic synthesis; multi-level synthesis; multi-output Boolean function; multi-output functions; multi-output implicants; Circuit synthesis; Feedback; Joining processes; Logic functions; Minimization methods;
Conference_Titel :
Field-Programmable Technology, 2002. (FPT). Proceedings. 2002 IEEE International Conference on
Print_ISBN :
0-7803-7574-2
DOI :
10.1109/FPT.2002.1188727
