Power minimization by clock root gating

Clock root gating transformation targets power savings on the clock tree by inserting gating logic at the root of the clock. In this paper, we propose an efficient graph-based algorithm to solve the root clock gating optimization problem. The algorithm is also tightly integrated with a clock tree synthesis tool so that real power savings can be achieved after the clock tree is generated. Experimental results on industrial circuits showed that significant power savings can be achieved.