Mapping of Embedded Applications on Hybrid Networks-on-Chip with Multiple Switching Mechanisms

This letter aims at optimizing the mapping of embedded applications on the hybrid network-on-chip (NoC) that intermingles multiple switching mechanisms. Specifically, we identify the critical characteristics of those switching mechanisms, deriving a new latency and energy model for this type of networks. A novel mapping scheme based on a branch-and-bound algorithm is proposed to map cores onto the NoC and allocate communications to different switching mechanisms simultaneously, such that the average communication latency and energy are optimized. A set of embedded applications are exploited for evaluation. Experimental results show that, compared with three existing mapping strategies, our mapping scheme can obtain considerable reductions in communication latency and energy on the hybrid NoC.