Architecture of a field-programmable VLSI processor using memory-based cells

This paper presents a field programmable VLSI based on a two-dimensional cell array and bit-serial architecture. Bit-serial architecture achieves high utilized ratio irrespective of the word length. Moreover, based on the regular data flow of bit-serial architecture, a lookup table implemented using a shift register is proposed for th cell. One of the arithmetic/logic, memory and control functions is selected in a cell. As a result, area of the cell is reduced.