Fast algorithms for designing multirate cascade filters

The design of a multirate cascade of discrete time filters using a FWLS (frequency-weighted least squares) approach is considered. The design strategy enables one to compensate at each stage for errors introduced by preceding stages in the cascade. As a result, very simple filters can be designed for the stages operating at higher sampling rates. A cascade FIR example is presented demonstrating how highly efficient decimators requiring large decimation rates can be designed. The example design yields a cascaded integrator comb (CIC) filter for the first stage. The design strategy applies to the design of interpolators and more arbitrary sample rate converters as well. Design of IIR cascade sections is also addressed.