Transient effects and characterization methodology of negative bias temperature instability in pMOS transistors

Author

Ershov, M. ; Lindley, R. ; Saxena, S. ; Shibkov, A. ; Minehane, S. ; Babcock, J. ; Winters, S. ; Karbasi, H. ; Yamashita, T. ; Clifton, P. ; Redford, M.

Author_Institution

PDF Solutions, San Jose, CA, USA

fYear

2003

fDate

30 March-4 April 2003

Firstpage

606

Lastpage

607

Abstract

We report a new effect - relaxation of pMOSFET degradation due to negative bias temperature instability (NBTI). "Apparent" NBTI degradation is reduced ("recovered") by as much as 30-50% after stress interruption, which can increase device lifetime by a factor of 10-30. Some problems associated with extrapolation of degradation with respect to time and stress voltage are also discussed.

Keywords

CMOS integrated circuits; MOSFET; extrapolation; life testing; semiconductor device reliability; semiconductor device testing; transient analysis; CMOS technologies; NBTI lifetime estimation; characterization methodology; device lifetime; negative bias temperature instability; pMOS transistors; pMOSFET degradation relaxation; reliability concern; stress interruption; stress voltage; time extrapolation; transient effects; voltage extrapolation; CMOS technology; Degradation; Life estimation; Lifetime estimation; MOSFETs; Negative bias temperature instability; Niobium compounds; Stress; Titanium compounds; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium Proceedings, 2003. 41st Annual. 2003 IEEE International

Print_ISBN

0-7803-7649-8

Type

conf

DOI

10.1109/RELPHY.2003.1197828

Filename

1197828