Title :
Identification of wafer defect clusters using a self-organizing multilayer perceptron
Author :
Huang, Chenn-Jung
Author_Institution :
Dept. of Comput. Sci. & Inf. Educ., Nat. Taitung Teachers Coll., Taiwan
Abstract :
During an electrical testing stage, each die on a wafer must be tested to determine whether it functions as it was originally designed. In the case of a clustered defect on the wafer, such as scratches, stains, or localized failed patterns, the tester may not detect all of the defective dies in the flawed area. To avoid the defective dies proceeding to final assembly, a testing factory must assign five to ten workers to check the wafers and hand mark the defective dies in the flawed region or close to the flawed region. This work proposes an automatic wafer-scale defect cluster identifier using a multilayer perceptron to detect the defect cluster and mark all the defective dies. The proposed work is also compared with an existing tool used in the industry. The experimental results verify that our proposed algorithm is very effective in defect identification and achieves better performance than the existing tool.
Keywords :
automatic testing; circuit analysis computing; integrated circuit manufacture; integrated circuit testing; multilayer perceptrons; wafer-scale integration; automatic wafer-scale defect cluster identifier; clustered defect; defective dies; electrical testing stage; localized failed patterns; multilayer perceptron; self-organizing multilayer perceptron; testing factory; wafer defect cluster identification; Assembly; Clustering algorithms; Dies; Filters; Multilayer perceptrons; Neural networks; Organizing; Production facilities; Shape; Testing;
Conference_Titel :
Neural Information Processing, 2002. ICONIP '02. Proceedings of the 9th International Conference on
Print_ISBN :
981-04-7524-1
DOI :
10.1109/ICONIP.2002.1198177