A reconfigurable 100 Mchip/s spread spectrum receiver

The flexibility of a reconfigurable receiver allows a system to be tailored to maximise the data rate over channels that vary from benign to those severely effected by multipath propagation. Accordingly a digital receiver based on field programmable gate arrays (FPGA) has been developed, with a burst-mode 100 Mchip per second (100 Mcps) direct sequence spread spectrum (DSSS) personality that targets a 10 Mbit/s data rate in extreme multipath scenarios. The design is based around a quadrature, two sample per chip baseband processing card that implements an asynchronous feedforward (interpolating) architecture. With this approach, system complexity resides solely in the receiver allowing the transmitter to be very small and cheap. This paper reviews the architecture and implementation of the receiver, and reports on some of the development and performance issues.