A radix-16 FFT algorithm suitable for multiply-add instruction based on Goedecker method

Author

Takahashi, Daisuke

Author_Institution

Inst. of Inf. Sci. & Electron., Tsukuba Univ., Ibaraki, Japan

Volume

2

fYear

2003

fDate

6-10 April 2003

Abstract

A radix-16 fast Fourier transform (FFT) algorithm suitable for multiply-add instruction is proposed. The proposed radix-16 FFT algorithm requires fewer floating-point instructions than the conventional radix-16 FFT algorithm on processors that have a multiply-add instruction. Moreover, this algorithm has the advantage of fewer loads and stores than either the radix-2,4 and 8 FFT algorithms or the split-radix FFT algorithm. We use Goedecker´s method to obtain an algorithm for computing radix-16 FFT with fewer floating-point instructions than the conventional radix-16 FFT algorithm. The number of floating-point instructions for the proposed radix-16 FFT algorithm is compared with those of conventional power-of-two FFT algorithms on processors with multiply-add instruction.

Keywords

fast Fourier transforms; floating point arithmetic; signal processing; Goedecker method; fast Fourier transform; floating-point instructions; multiply-add instruction; processors; radix-16 FFT algorithm; Computer aided instruction; Computer architecture; Costs; FETs; Fast Fourier transforms; Flexible printed circuits; Fourier transforms; Libraries; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 2003. Proceedings. (ICASSP '03). 2003 IEEE International Conference on

ISSN

1520-6149

Print_ISBN

0-7803-7663-3

Type

conf

DOI

10.1109/ICASSP.2003.1202454

Filename

1202454