Architectural design and analysis toolbox to implement shortest path algorithms in hardware

The theoretical complexity analysis of shortest path algorithms has always been a focus research area. Nevertheless, the algorithms run inefficiently in microprocessor-based systems. As embedded systems gain popularity, high-performance, low-cost and low-power solutions are imperative. This can be achieved by porting the complex algorithms to architectures. To compare the performance of these algorithms in hardware, an Architectural Design and Analysis Toolbox is proposed. We show that this approach benefits from architectural optimisation opportunities that reduce the execution time by up to 50%.