Performance optimization in micro-power, low-voltage log-domain filters in pure CMOS technology

The effect of parasitic capacitance on a basic building block of pure CMOS log-domain filters is discussed in this paper. The drawn analysis clearly highlights a basic trade-off between the system dynamic range and its bandwidth and helps to single out a design solution that optimizes the circuit performance. Such a procedure is exemplified with the design of a third order log-domain low-pass filter, operating in class AB. The circuit is fully integrated in a pure 0.8 μm CMOS technology, including signal compressor and expander, and operates down to 1.2 V. The dynamic range is larger than 51 dB and the whole circuit dissipates less than 70 μA.