An improved binary algorithmic A/D converter architecture

A method to reduce the accumulation of the systematic errors in cyclic and pipelined A/D converters is proposed. The method implies small changes to the known configurations and can achieve an error reduction of about three times. The results of this method are also compared to those from architectures based on Gray coding which employs a similar approach and the well known binary converters. The system level simulations show that the new method has significant advantages over binary coding and it performs close to the Gray technique.