A time-interleaved switched-capacitor band-pass delta-sigma modulator

A band-pass delta-sigma modulator (BPDSM) is a key building block of a digital intermediate frequency (IF) of a wireless communication. A BPDSM is difficult to implement with switched-capacitor (SC) circuits at high IF frequencies due to the high clock rate requirement. This paper proposes a time-interleaved (TI) SC BPDSM architecture that can operate at higher frequency than the conventional BPDSM architecture. The proposed 5-stage TI architecture with recursive feedback loop provides a reduction in the clock frequency requirement by a factor of 5 and relieves the settling time requirement to one-fourth of what the same period. The test chip was designed and fabricated for a 30 MHz IF system with a 0.35-μm CMOS process. The measured peak SNR for a 200-kHz bandwidth is 63 dB while dissipating 75 mW and occupying 1.3 mm².