A 10-bit, 4 mW continuous-time sigma-delta ADC for UMTS in a 0.12 μm CMOS process

A 10bit-resolution continuous-time single-bit ΣΔ ADC for UMTS is introduced. A power-efficient implementation of a 2^nd-order single-bit modulator is presented: analog non-idealities are compensated at system level, in order to relax the specs of the analog components, reducing power-drain. Clocked at 256 MHz, the 0.12 μm CMOS ΣΔ ADC achieve´s 60 dB peak SNR over a 2 MHz signal bandwidth, consuming 4mW at 1.2 V supply.