DocumentCode
396467
Title
A memory efficient realization of cyclic convolution and its application to discrete cosine transform
Author
Chen, Hun-Chen ; Jiun-In Gu ; Jen, Chein-Wei
Author_Institution
Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsin-Chu, Taiwan
Volume
4
fYear
2003
fDate
25-28 May 2003
Abstract
This paper presents a memory efficient design for realizing the cyclic convolution and its application to the discrete cosine transform (DCT). We adopt the method of distributed arithmetic computation, and exploit the symmetry property of DCT coefficients to merge the elements in the matrix of the DCT kernel and then separate the kernel to be two perfect cyclic forms to facilitate an efficient realization of 1-D N-point DCT using (N-1)/2 adders or subtractors, one small ROM module, a barrel shifter, and N-1/2+1 accumulators. The comparison results with the existing designs show that the proposed design can reduce delay-area product significantly.
Keywords
CMOS logic circuits; convolution; discrete cosine transforms; distributed arithmetic; performance evaluation; read-only storage; DCT coefficients; ROM module; TSMC CMOS data-path cell-library; adders; cyclic convolution; delay-area product reduction; discrete cosine transform; distributed arithmetic computation; memory efficient design; subtractors; symmetry property; Application software; Arithmetic; Computer architecture; Convolution; Design engineering; Discrete cosine transforms; Distributed computing; Hardware; Kernel; Read only memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN
0-7803-7761-3
Type
conf
DOI
10.1109/ISCAS.2003.1205766
Filename
1205766
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