Title :
Implementation of a parallel turbo decoder with dividable interleaver
Author :
Kwak, Jaeyoung ; Park, Soak Min ; Yoon, Sang-Sic ; Lee, Kwyro
Author_Institution :
EECS, Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
Abstract :
In this paper, VLSI architecture for an efficient turbo decoder with parallel architecture has been studied to achieve high-throughput. For 100% PE utilization, a dividable interleaving method is proposed, which not only solves the memory conflict problem in extrinsic information memory, but also reduces the required memory for interleaver. We mapped the proposing parallel turbo decoder with 4 SISO´s and a dividable S-random interleaver with 0.35 μm CMOS technology, which occupies 21.6 mm2, supports up to 41.8 Mb/s decoding rate.
Keywords :
CMOS integrated circuits; VLSI; decoding; interleaved storage; parallel architectures; turbo codes; 0.35 micron; 41.8 Mbit/s; CMOS technology; SISO mapping; VLSI architecture; dividable interleaver; memory conflict; parallel turbo decoder; CMOS technology; Computational complexity; Delay effects; Hardware; Interleaved codes; Iterative algorithms; Iterative decoding; Pipeline processing; Registers; Turbo codes;
Conference_Titel :
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
0-7803-7761-3
DOI :
10.1109/ISCAS.2003.1205889
