A low power 4.3 GHz phase-locked loop with advanced dual-mode tuning technique including I/Q-signal generation in 0.12 μm standard CMOS

The design of a 4.3 GHz Integer-N (Int-N) frequency synthesizer fabricated in a 0.12 μm standard CMOS-technology for a direct conversion UMTS receiver is reported. The fully-integrated, differential, complementary, LC-tuned voltage controlled oscillator (LC-VCO) can be tuned from 4.22 GHz to 4.34 GHz with 400 kHz steps. In order to support QPSK modulation process for the UMTS receive-band (2.11 GHz - 2.17 GHz), I/Q-signals are generated using a divide-by-two stage in master-slave configuration. The proposed advanced dual-mode tuning technique is based on digital coarse-tuning with subsequent analog fine-tuning. Coarse-tuning is controlled by an additional digital logic. The latter tuning phase is done by a conventional charge pump phase-locked loop (PLL). The 2^nd order loop filter is realized off-chip. Except for the VCO with 2.3 V and a current consumption of 2 mA to achieve higher output swing, the system is biased from a 1.5 V supply consuming 8 mA. Thus, the overall power consumption can be stated to be less than 17 mW. The low power consumption compares favorable with previously published synthesizers.