Title :
A virtually jitter-free fractional-N divider for a Bluetooth radio
Author_Institution :
Philips Semicond., Zurich, Switzerland
Abstract :
Using a fractional-N PLL as a modulator in a transmitter has gained great interest recently. In order to maintain or even improve the performance of the transmitter, the jitter of the PLL has to be kept low. When a power-efficient zipper divider is employed in the PLL, its jitter must be considered because of jitter accumulation and scaling in the divider. Trying to apply the proven direct reclocking technique to combat jitter fails here due to the asynchronous nature of the zipper divider. This fact motivates us to devise a new and very effective technique called. double-reclocking to remove jitter. It is demonstrated that the double-reclocking is even able to remove jitter that is too large for the direct reclocking scheme, if it worked here, to cope with.
Keywords :
Bluetooth; CMOS integrated circuits; asynchronous circuits; frequency dividers; jitter; mixed analogue-digital integrated circuits; phase locked loops; radio transmitters; synchronisation; Bluetooth radio; CMOS transceiver; PLL jitter; asynchronous divider; double-reclocking; fractional-N PLL; jitter removal; jitter-free fractional-N divider; power-efficient zipper divider; transmitter; Bluetooth; Circuits; Clocks; Communication industry; Costs; Frequency conversion; Manufacturing; Phase locked loops; Radio transmitters; Timing jitter;
Conference_Titel :
Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on
Print_ISBN :
0-7803-7761-3
DOI :
10.1109/ISCAS.2003.1205969