Parallel sub-convolution filter bank architectures

This paper provides an overview of the design and properties of parallel discrete-time filter bank architectures based on the concept of frequency-domain sub-convolution developed by the author. It is demonstrated that this lossless filter bank method is an excellent choice for implementing many signal processing functions in real-time high rate systems. These filter bank architectures incorporate vector processing, the discrete Fourier transform-inverse discrete Fourier transform (DFT-IDFT) overlap-and-save convolution method, and the sub-convolution method. The parallel processing architectures presented facilitate processing for very high rate sampled systems (multi-giga-samples per second) with lower rate CMOS hardware with relatively low complexity (low transistor count). Complexity comparisons demonstrate that the sub-convolution filter bank results in less complex concurrent implementations than parallel time-domain convolution and conventional frequency-domain convolution methods for many processing rate reductions and filter orders. In addition, the sub-convolution filter bank may be used to provide intermediate computation gain, with computation requirements lying in between those of these two conventional methods. As such, the parallel sub-convolution filter bank may also be useful in low-power hardware realizations.