Dual clock rate block data parallel architecture [multiprocessor based FIR filter example]

This paper presents a multiprocessor system with a dual clock rate. We used the block data overlap-save algorithm and the block data parallel architecture (BDPA) to implement a two dimensional (2D) FIR filter. We were able to significantly improve the performance of the block data parallel architecture (BDPA) multiprocessor system by using a dual rate clock as compared to the performance using a single rate clock. We designed a 2D-FIR filter system with a four processor module array to demonstrate the improvement in performance. It had a throughput performance of 7.975 samples per processor clock cycle and the processor utilization was 78.53%.