Title :
Reducing power consumption in FPGA routing
Author :
Zamani, Morteza Saheb ; Esmaili, Ehsan
Author_Institution :
Dept. of Comput. Eng., Amirkabir Univ. of Technol., Iran
Abstract :
One of the major drawbacks of field programmable gate arrays is their poor energy efficiency. This paper focuses on the routing phase of FPGA design and attempts to optimize dynamic power consumption in FPGA interconnect. Power optimization is performed with small side effects on circuit performance and area. Our enhancements to the VPR timing driven algorithm reduced the FPGA routing power by about 10% with negligible loss in circuit performance.
Keywords :
circuit optimisation; field programmable gate arrays; network routing; power consumption; FPGA routing; circuit performance; cost function; field programmable gate arrays; power consumption reduction; power optimization; timing driven algorithm; Circuit optimization; Delay effects; Design optimization; Energy consumption; Field programmable gate arrays; Integrated circuit interconnections; Optical computing; Power engineering and energy; Power engineering computing; Routing;
Conference_Titel :
Electrical and Computer Engineering, 2003. IEEE CCECE 2003. Canadian Conference on
Print_ISBN :
0-7803-7781-8
DOI :
10.1109/CCECE.2003.1226332
