Synthesis of a 12-bit complex mixer for FPGA implementation

Author

Liu, Qian ; Langlois, J.M.P. ; Al-Khalili, D. ; Szwarc, V. ; Ink, R.

Author_Institution

Royal Military Coll. of Canada, Kingston, Ont., Canada

Volume

1

fYear

2003

fDate

4-7 May 2003

Firstpage

81

Abstract

This paper presents a FPGA implementation of a multiplier-based complex mixer for communication systems that require high-throughput rates and architecture scalability. The paper focuses on the design of a complex mixer that consists of a Baugh-Wooley-adder-tree complex multiplier and a direct digital frequency synthesizer (DDFS) based on a linear segment interpolation algorithm. The regular structure of this architecture permits deep pipelining and facilitates scaling to meet a given system specification.

Keywords

direct digital synthesis; field programmable gate arrays; interpolation; mixers (circuits); Baugh-Wooley-adder-tree complex multiplier; FPGA implementation; architecture scalability; direct digital frequency synthesizer; linear segment interpolation algorithm; multiplier-based complex mixer; Band pass filters; Baseband; Clocks; Field programmable gate arrays; Frequency synthesizers; Interpolation; Signal generators; Signal processing; Signal processing algorithms; Wideband;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2003. IEEE CCECE 2003. Canadian Conference on

ISSN

0840-7789

Print_ISBN

0-7803-7781-8

Type

conf

DOI

10.1109/CCECE.2003.1226349

Filename

1226349