DocumentCode
397237
Title
A run-time word-level reconfigurable coarse-grain functional unit for a VLIW processor
Author
Busa, Natalino G. ; Sala, Carles Rodoreda
Author_Institution
Philips Res. Labs., Eindhoven, Netherlands
fYear
2002
fDate
2-4 Oct. 2002
Firstpage
44
Lastpage
49
Abstract
Nowadays, new DSP applications are offering combined and flexible multimedia and telecom services. VLIW processor architectures, which include dedicated but inflexible functional units, are usually tuned to a single specific application. In order to accelerate a wide range of applications, we propose a VLIW processor containing a novel run-time reconfigurable functional unit (RC-FU). Only a few hundred bits and few cycles are necessary to configure a new coarse-grain operation on the RC-FU unit. After reconfiguring its internal datapath and microprogram, the RC-FU can execute a number of look-alike DSP functions, such as 8-point DCT or 4-point FFT. The RC-FU itself is a VLIW processor and the configuration contexts are generated using a high-level synthesis tool. The proposed RC-FU provides high processing power and can be efficiently tuned to the requirements of a variety of DSP applications.
Keywords
high level synthesis; parallel architectures; reconfigurable architectures; VLIW processor; architectural synthesis; configuration contexts; high-level synthesis; reconfigurable functional unit; Acceleration; Adders; Computer applications; Computer architecture; Delay; Digital signal processing; Field programmable gate arrays; Hardware; Runtime; VLIW;
fLanguage
English
Publisher
ieee
Conference_Titel
System Synthesis, 2002. 15th International Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
1-58113-576-9
Type
conf
Filename
1227150
Link To Document