Title :
Energy/power estimation of regular processor arrays
Author :
Derrien, Steven ; Rajopadhye, Sanjay
Author_Institution :
IRISA, Rennes, France
Abstract :
We propose a high-level analytical model for estimating the energy and/or power dissipation in VLSI processor (systolic) array implementations of loop programs, particularly for implementations on FPGA based CO-processors. We focus on the respective impact of the array design parameters on the overall off-chip I/O traffic and the number and sizes of the local memories in the array. The model is validated experimentally and shows good results (12.7% RMS error in the predictions).
Keywords :
field programmable gate arrays; high level synthesis; logic partitioning; systolic arrays; FPGA; VLSI processor; VLSI processor array; design space exploration; processor array partitioning; programmable logic; systolic array; Analytical models; Embedded system; Energy consumption; Field programmable gate arrays; Kernel; Logic design; Power dissipation; Power system modeling; Programmable logic arrays; Very large scale integration;
Conference_Titel :
System Synthesis, 2002. 15th International Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
1-58113-576-9
