Title :
High-speed error correcting code LSI with throughput of 5 to 48 Gbps
Author :
Hamasuna, Yuuichi ; Hata, Masayasu ; Takumi, Ichi
Author_Institution :
DDS Inc., Nagoya, Japan
fDate :
29 June-4 July 2003
Abstract :
We proved that the hardware implementation of the proposed code and the new packet synchronization system was effectively realized by using a unique circuit configuration. A three-dimensional size-five coder and decoding-synchronization system was implemented on FPGA. The developed FPGA was applied to a high-speed MPEG communication device, which can transmit a movie signal of 20 Mbps.
Keywords :
data compression; error correction codes; field programmable gate arrays; large scale integration; packet switching; 20 Mbit/s; 5 to 48 Gbit/s; FPGA; LSI; MPEG communication device; decoding-synchronization system; high-speed error correcting code; packet synchronization system; three-dimensional size-five coder; Bit error rate; Clocks; Decoding; Error correction codes; Field programmable gate arrays; Large scale integration; Parity check codes; Performance loss; Synchronization; Throughput;
Conference_Titel :
Information Theory, 2003. Proceedings. IEEE International Symposium on
Print_ISBN :
0-7803-7728-1
DOI :
10.1109/ISIT.2003.1228489
