Title :
Weighted order statistic image filter chip based on cellular neural network architecture
Author_Institution :
Inst. of Electron., Lodz Tech. Univ., Poland
Abstract :
This paper describes a VLSI chip of an analog image weighted order statistic (WOS) filter based on cellular neural network (CNN) architecture for real-time applications. The chip has been implemented in CMOS AMS 0.8 μm CYE technology. This filter consists of feedforward nonlinear template B operating within the window of 3 by 3 pixels around the central pixel being filtered. The feedforward nonlinear CNN coefficients have been realized using programmable nonlinear coupler circuits. The WOS filter chip allows for processing of images with 300 pixels horizontal resolution. Functional tests of the chip have been performed using a special test set-up for PAL composite video signal processing. Using the set-up real images have been filtered by WOS filter chip under test.
Keywords :
CMOS integrated circuits; VLSI; cellular neural nets; coupled circuits; feedforward neural nets; image resolution; nonlinear filters; programmable logic arrays; real-time systems; statistics; video signal processing; 0.8 microns; CMOS AMS CYE technology; PAL composite video signal processing; VLSI chip; analog image; cellular neural network architecture; feedforward nonlinear CNN coefficient; feedforward nonlinear template; image processing; nonlinear filter; pixel horizontal resolution; programmable nonlinear coupler circuit; real image; real-time applications; weighted order statistic image filter chip; CMOS technology; Cellular neural networks; Circuit testing; Coupling circuits; Filters; Image resolution; Pixel; Signal resolution; Statistics; Very large scale integration;
Conference_Titel :
Image Processing, 2003. ICIP 2003. Proceedings. 2003 International Conference on
Print_ISBN :
0-7803-7750-8
DOI :
10.1109/ICIP.2003.1246745