DocumentCode
398842
Title
Self-positioning digital window comparators for mixed-signal DfT
Author
Venuto, D. De ; Ohletz, M.J. ; Ricco, Bruno
Author_Institution
Politecnico di Bari, Italy
Volume
1
fYear
2003
fDate
16-19 Sept. 2003
Firstpage
438
Abstract
The use of simple digital window comparators for the on-chip evaluation of analogue signals is described. It is shown that a window can be created by choosing different gate input configurations. The potential problem of lot-to-lot variation of the comparator window position can be compensated by an on-chip repositioning technique. The components for the implementation comprise of a reference comparator and the evaluation comparators that are described along with the implementation of the technique. It is shown, that this technique allows the automatic lot condition adjustment for the evaluation comparator windows. The technique can optionally provide lot condition diagnostics for the test record as well as diagnosis of the actual window selection of the evaluation comparator.
Keywords
comparators (circuits); design for testability; logic gates; mixed analogue-digital integrated circuits; analogue signals; automatic lot condition adjustment; comparator window position; design for testability; evaluation comparators; gate input configurations; lot condition diagnostics; lot-to-lot variation; mixed signal DfT; on-chip evaluation; on-chip repositioning; reference comparator; self-positioning digital window comparators; Ambient intelligence; Circuit testing; Clocks; Costs; Design optimization; Digital integrated circuits; Integrated circuit reliability; Logic gates; Time to market; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Emerging Technologies and Factory Automation, 2003. Proceedings. ETFA '03. IEEE Conference
Print_ISBN
0-7803-7937-3
Type
conf
DOI
10.1109/ETFA.2003.1247740
Filename
1247740
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