SoC implementation issues for synthesizable embedded programmable logic cores

As integrated circuits have become more and more complex, the ability to make post-fabrication changes will become more and more attractive. This ability can be realized using programmable logic cores. Currently, such cores are available from vendors in the form of a "hard" layout. An alternative approach is to use a "soft", or synthesizable programmable logic core that can be synthesized using standard library cells. In this paper, we describe the design of an integrated circuit that incorporates such a synthesizable programmable logic core. We focus on implementation issues that arose; specifically, the choice of core size, the connection of the core to the rest of the integrated circuit, and clock tree synthesis. We also present area and delay overhead results.