A substrate noise analysis methodology for large-scale mixed-signal ICs

Author

Chu, Wen Kung ; Verghese, Nishath ; Heayn-Jun Cho ; Shimazaki, Kenji ; Tsujikawa, Hiroyuki ; Hirano, Shouzou ; Doushoh, Shirou ; Nagata, Makoto ; Iwata, Atsushi ; Ohmoto, Takafumi

Author_Institution

Cadence Design Syst. Inc., San Jose, CA, USA

fYear

2003

fDate

21-24 Sept. 2003

Firstpage

369

Lastpage

372

Abstract

A substrate noise analysis methodology is described that simulates substrate noise waveforms at sensitive locations of large-scale mixed-signal ICs. Simulation results for a 7.3 mm×7.3 mm chip with 500 k devices, obtained in a few hours on an engineering server, show good correlation with silicon measurements as testing conditions are varied. An analysis of the substrate and package reveals the importance of modeling inductive coupling between neighboring switching and quiet ground pins due to the substrate return of currents between them.

Keywords

circuit simulation; coupled circuits; integrated circuit modelling; integrated circuit noise; interference (signal); mixed analogue-digital integrated circuits; 7.3 mm; inductive coupling; large-scale mixed-signal IC; quiet ground pins; sensitive location noise simulation; substrate noise analysis methodology; substrate noise waveforms; substrate return currents; switching pins; Circuit noise; Circuit simulation; Information analysis; Integrated circuit noise; Large-scale systems; Noise measurement; Packaging; Semiconductor device measurement; Switching circuits; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003

Print_ISBN

0-7803-7842-3

Type

conf

DOI

10.1109/CICC.2003.1249420

Filename

1249420